A memory of a computer system may include a table including a mapping of input/output (I/O) addresses and real addresses to enable translation between the input/output and real addresses. The computer system may include an address cache (e.g., a translation lookaside buffer (TLB)) for locally storing frequently accessed entries from the translation table.
Upon completion of an I/O operation, one or more entries in the translation table and TLB may need to be invalidated. Conventional methods and apparatus for invalidating TLB entries are costly because they adversely affect system performance since they require an invalidation operation for each address cache entry. Further, another method of snooping all memory writes to a translation table and then invalidating corresponding address cache entries requires a large amount of chip real estate. Accordingly, improved methods and apparatus for invalidating address cache entries are desired.